Simulating solutions – nanotransistors
Computer models that simulate silicon chip production are helping manufacturers develop next generation transistors at 32 and 22nm nodes and beyond.
Several of these models – developed at the Fraunhofer Institute for Integrated Systems and Device Technology in Erlangen, Germany – are being incorporated into a commercial simulation package offered by Synopsys, based in Mountain View, USA. STMicroelectronics, a major European microchip manufacturer, has validated the work.
Chip manufacturers routinely use technology computer aided design (TCAD) to model product fabrication, before selecting the most promising techniques and materials. But existing software models are at the limits of their capabilities with the emerging generation of smaller chips.
‘Technology computer aided design can cut costs by about 40%,’ explains Fraunhofer’s Dr Peter Pichler. But he says existing models are not feasible for 22nm technology, while his team’s models will work down to 20nm and smaller.
For the last four years, he has co-ordinated an EU-funded project called ATOMICS, which has created simulations of emerging processes that are being used to miniaturise electronics. Physical samples have been tested in over 200 experiments, and the results validated against those obtained by computer modelling.
A number of physical effects govern the behaviour of silicon chips. For example, trace amounts of elements such as phosphorus or arsenic can be added to modify its electrical behaviour.
In order to work faster, next-generation chips will need higher dopant concentrations. However, the process to embed them via ion implantation is damaging, and the wafer must be ‘repaired’ by annealing. The miniaturisation process also makes chips more thermally sensitive so they must be annealed quickly using new techniques such as flash annealing that reduce the process time from seconds to milliseconds.
A model that simulates these cycle times was released in the latest version of Sentaurus Process – a simulation package from Synopsys.
‘Nobody had modelled flash annealing before,’ says Pichler. ‘We did it because we knew it would be helpful for next generation chips.’
The software can also model new materials – such as silicon-germanium alloys, which ‘did not exist five years ago’ – and new structures, such as strained silicon, which increases the mobility of charge carriers along certain crystal directions in order to boost current.
ATOMICS has simulated several poorly understood effects of strained silicon, such as electron diffusion to the neighbouring silicon/germanium layer.
A number of research teams have developed extended simulation models, but Pichler believes that his have the edge.
‘The semiconductor industry wants to have these models integrated and implemented into commercial software tools – and that’s what we have done with Synopsys,’he says.
Of the 12 models developed by ATOMICS, six have already been incorporated into the Sentaurus Process, including those of end of range (EOR) defects, such as dislocation loops and boron trapping. Other models of stress and strain effects on activation and diffusion are due to be introduced next year, alongside those of EOR defects in silicon/germanium. STMicroelectronics is already applying them for 22nm technology.