Silicon rising in the energy sector

Materials World magazine
,
27 Feb 2019

Shashi Paul of the Emerging Technologies Research Centre at De Montfort University, UK, discusses using silicon nano-structures for energy-related and electronic devices.   

Silicon, as an electronic material, has played an enormous role in promoting the modern technical evolution in almost all fields. And, needless to say, it will continue its leadership until a better material is found. We are currently going through an exploration period to search out alternative materials. A numer of different materials are have been proposed as challengers, but silicon (Si) is still the front runner, as far as complementary metal-oxide-semiconductor (CMOS) technologies is concerned.   

Silicon is widely used in electronic industries in a number of forms, such as the amorphous silicon used in thin-film transistors (TFTs) in liquid-crystal display units, poly-silicon can be found in flash memory structures and photovoltaic solar cells, and single crystals are predominately used in CMOS technologies.

Among the various forms of silicon embodiments, silicon nano-structures – for example, silicon nanowires – are also currently being explored, and for the last a few decades, there has been intense interest in how to prepare nanometre scale silicon.

Small-scale research

Electrical, optical and mechanical properties exhibited in nano-sized materials are not commonly observed in bulk. Numerous applications of silicon nano-structures have been proposed in literature, but the use of such structures in electronic devices has not yet penetrated the consumer electronics market.

The scientific knowledge behind making single crystal silicon is well-established and these crystals have been exploited in various electronic devices, including diodes, transistors, and memory devices.

But there is still active research going on in the development of silicon poly-crystalline strucutres that range from a few nanometres to hundreds of micrometres, at low temperature, improving the stability of amorphous hydrogenated silicon (a-Si:H) in thin-film transistors (TFTs) and depositing a-Si:H at low temperature (<300°C).

However, a-Si:H is continuing to suffer from inherent instability in spite of a number of suggestions for improvements. The great attractiveness of amorphous silicon is low deposition temperature, thus it is compatible with glass and flexible substrates, including some special plastic substrates. Is there an alternative method that can deposit crystalline structures at low temperatures? A number of new methods have been proposed for the growth of silicon crystalline structures  and most of them, generally, focus on nano-structures, such as silicon nano-wires. The vapour liquid solid (VLS) technique is a commonly used method.

In this method, a metal is utilised as a template to grow such nano-structures, and gold is one of the most explored metals for this role. A thin layer, of a few nanometres of gold, is evaporated on the silicon substrate which is backed by a thin oxide. After annealing the gold-coated substrate at an appropriate temperature, the clusters of gold result in nano particles on the surface of the substrate. Next, this substrate with the gold (Au) nano particles on it is placed in the vapour environment of a silicon-containing gas (e.g. SiH4) in the chemical vapour deposition (CVD) or plasma-enhanced chemical vapour deposition (PECVD) chamber.

The wires start growing by the VLS method. However, use of gold is subject to a serious shortcoming. The deposition temperature required to grow nanowires of silicon is more than 300°C in the VLS technique. The eutectic temperature of the Si-Au system is around 363°C. This implies that gold is allowed to diffuse into the nanowire/nano-structures – this is highly undesirable from the point of view of device reproducibility and reliability. It has been shown that gold is always present on the surface of silicon-nanowires.

Therefore, if we really would like to exploit the true potential of these structures, we should select a metal
in such a way that the growth temperature should be lower than the metal-silicon eutectic temperature, as well as being compatible with glass and flexible substrates to make them usable in future foldable/flexible consumer electronics.

Choice of metals

The choice of the metal that is to be used as the template in this VLS technique for growing silicon nanowires is dependant on the eutectic temperature of the metal-Si system. Unfortunately, gold is a poor choice for the metal element, as the eutectic temperature of gold falls much below the ambient temperature in this deposition technique. The case for gold is made further worse by the fact that the trap level generated by gold in silicon is very near to the midgap of Si. This implies that the recombination rate approaches a maximum as the energy level of the recombination centre approaches midgap.

Metals with impurity level energies close to the conduction or valence band will cause doping. In particular, gallium (Ga), aluminium (Al) and indium (In) have acceptor levels close to the valence band so will cause p-type doping. Similarly, antimony (Sb), lithium (Li) and bismuth (Bi) can cause n-type doping. The materials that are close to the middle of the energy bandgap, such as gold, zinc (Zn), copper (Cu), iron (Fe), chromium (Cr), palladium (Pd) or cobalt (Co), should not be the first choice if deep impurity levels are not desired. However, for charge storage, deep level energy states can be ideal candidates for a long retention for solid-state transistor-based electronic memory devices, for example, flash memory.

Planning for problems

The drawback of using Al metal is its high oxygen sensitivity. Cadmium (Cd) and Bi has a relatively high vapour pressure, which means the metal may also evaporate during the growth process, rather than having a catalytic effect on the growth. In that case, even a few atoms can compromise the performance of the device. Ga is also unfavourable because it has a very low melting and eutectic point (30°C). It melts and tends to migrate on the sample’s surface, making the size and position control of the catalyst very difficult.

Silver (Ag) has a high eutectic temperature (845°C), therefore it is not compatible with temperature-sensitive substrates and low-temperature processes. Hence, tin (Sn), platinum (Pt), nickel (Ni), Pd and titanium (Ti) could be possible options of catalyst material for silicon nanostructures growth via a VLS mechanism if high self-doping is to be avoided. But the eutectic temperature for Pt, Pd and Ti with Si is higher than 750°C. Ti has been used as a template material to grow the silicon nanowires – Ti-coated substrate was annealed at 920°C and then wires were grown at 670°C.

Making it work

Over the last few years, there has been a concerted effort to use alternative metal catalysts, such as Sn and In, for the growth of silicon nano-structures at low temperature via VLS technique. But both of these metal catalysts form shallow energy defect levels because their eutectic temperatures are less than 250°C and can easily be diffused into silicon. To overcome this problem, other metals need to be resorted to, such as Ti, Pd, Ni and Pt. These metals don’t form trap levels near the midgap. Their eutectic temperatures are higher than 750oC, which eliminates the possibility of diffusion of metal into Si if the growth temperature is much lower than the eutectic temperature.

But the growth temperatures for the growth Si-structures via VLS technique exceeds 600°C, which results in very high thermal budgets and hence the process is not compatible with cheap and flexible substrates. Therefore, one must find an alternative growth method to VLS. Using a combination of pre-growth preparation steps and plasma-enhanced chemical vapour deposition (PECVD), we have demonstrated the growth of silicon structures, micro and nano-sized, at ≤ 350°C.  Using this process, we have been able to grow silicon structures on plastic/glass substrates and have demonstrated their use in photovoltaic solar cells and electronic memory devices.

Although, before silicon nano-structures can be integrated into a commercial product, such as consumer plastic electronics, batteries or solar cells, there are still major challenges to conquer. These include establishing environmentally friendly growth/deposition processes, growth of 100% crystalline structures on glass and plastic substrates, minimising surface energy states,  understanding doping in nano-structures from metal catalysts, selection of appropriate metal catalysts depending upon the application, and pre-planned recycling methods of Si-devices, once their use become redundant, to reduce any environmental impact.