A junctionless silicon nanowire transistor that could improve the performance of microchip technology has been formed by researchers in Ireland.

The patented transistor is based on the use of a silicon nanowire controlled by a silicon gate. The gate modulates the resistance of the nanowire to squeeze the electron channel and turn off the device. Ion doping produces p-type (boron) and n-type (arsenic) field-effect transistors (FETs). In both cases, the wire is separated from the gate by a silicon dioxide insulator. The device has been fabricated using electron beam lithography on silicon-insulator wafers.

The most common type of junction is the p-n junction, that is formed by the contact between a p-type piece of silicon, doped to create holes, and an n-type piece of silicon, doped to create electrons. Traditional transistors contain two p-n junctions.

Professor Jean-Pierre Colinge at the Tyndall National Institute, University College Cork, Ireland, explains, ‘The advantage of using no junction to conventional FETs, is that the doping concentration is kept constant throughout the device, and as a result diffusion of doping atoms is minimised’.

He continues, ‘We found that if the dimensions are small enough you don’t really need junctions. Creating high-quality junctions at the [nanoscale] can be a challenge. By eliminating a junction, doping concentration can be more controlled, speeding up the process of fabricating smaller transistors on a regular basis’, notes Colinge.

a: Scanning electron microscope of a device with three parallel nanowires sharing a common gate electrode, b: Three silicon nanowires and the common gate electrode, c: A single silicon nanowire.

The team of scientists at UCC have created n-type and p-type junctionless silicon field-effect transistors with a channel length of one micrometre, with a nanowire cross-section of about 10nm by 30nm. A smaller transistor with a 50nm channel length and a cross-section of 8nm by 12nm has now been fabricated.

Another key benefit to the junctionless transistor is that it could eliminate shortchannel effects. Improving overall efficiency by 30%, by switching from off to on at a lower voltage. This is a result of the low value of the sub-threshold slope in the transistor design. So far, results have revealed the short-channel effect to be small, with the devices showing a sub-threshold slope of 60mV per decade and a draininduced barrier lowering (DIBL) of 7mV.

Specialist in semiconductor materials Professor Christopher Snowden at the University of Surrey, UK, says, ‘The 50nm itself, while being an important development is in fact comparable with standard complementary-metal–oxide–semiconductor technology gate lengths found in most microprocessors (which are 45nm). However, improving the efficiency of transistor operation and reducing thermal dissipation are extremely important in the future evolution of integration technologies. This type of technology could prove effective’.

The fabricated prototype has been entered under the EU seventh framework programme.

Further information

www.sqwire.eu