Growing up with nanowires
European researchers have devised a technology for ‘growing’ nanowires in a vertical configuration, which they say could lead to smaller, faster and more energy-efficient computer microchips
The Nanowire-based One-Dimensional Electronics (NODE) project focused on combining silicon nanowires with indium arsenide and germanium substrates to overcome previous problems of using a gold catalyst. ‘The epitaxy of silicon nanowires from gold particles is difficult to control in terms of nanowire directionality, making it difficult to have high yield in vertical devices. There is also the concern of gold-contamination of CMOS processes,’ says Claes Thelander, Professor of Solid State Physics at Lund University, Sweden, a partner of the project.
Being able to control the direction of growth means that researchers can tune various physical properties such as bandgap, refraction index, thermal and electrical conductivity, and piezoelectric polarisation.
This concept looked at hybrid technology based on the formation of silicon nanowires by etching, followed by epitaxial growth of, for instance germanium.
‘But silicon technology becomes very challenging when you get down to 10-15nm,’ explains his colleague Lars Samuelson, Director of the Nanometer Structure Consortium at Lund University and coordinator of the NODE project.
‘One of the problems of the top-down approach is that it introduces harsh environments and you end up with devices that may be dominated by defects.’
The NODE researchers dry etch hole patterns on silicon for constrained growth of nanowires, without using a catalyst. A template is prepared by lithography patterning of a plasma-enhanced chemical-vapour deposited 300nm silicon oxide film stack with openings to expose the underlying silicon. The etching technique can shrink printed feature sizes thanks to a polymeric coating deposited on the developed resist. Particular care is taken to clean the side walls and the bottom silicon substrate to avoid defects during growth.
‘We call it “guided self-assembly”, and it gives more uniform nanowire surfaces,’ says Samuelson. ‘Vertical nanowires can consist of different materials, by altering the depositing material, so the wire takes on layers with different characteristics.’
This vertical arrangement may be the route to 3D circuit design as well as monolithic on-chip optoelectronics.
X-ray diffraction gives information about crystallo-graphic phases, stacking defects and epitaxial relationships with orientation distributions.
Electronics giant IBM Research, based in Rüschlikon, Switzerland, one of many partners on the project, stresses that they are still some way from seeing the technology in application.
‘Good control over wire growth has been achieved, but further processing is required to
integrate nanowires into functional devices,’ explains Dr Heike Riel, Manager of Nanoscale Electronics at IBM Research.
‘After growth, the wire surface needs to be properly passivated by thermal oxidation by conformal atomic layer deposition of a high-K material serving as gate dielectric.
‘Nanowire technology will gradually find its place by offering advantages such as the potential for wrap gates, 3D integration, and the ability to grow heterostructures of materials with large lattice mismatch.’Materials World Magazine, 01 Mar 2010
The Nanowire-based One-Dimensional Electronics (NODE) project focused on combining silicon nanowires with indium arsenide and germanium substrates to overcome previous problems of using a gold catalyst. ‘The epitaxy of silicon nanowires from gold particles is difficult to control in terms of nanowire directionality, making it difficult to have high yield in vertical devices. There is also the concern of gold-contamination of CMOS processes,’ says Claes Thelander, Professor of Solid State Physics at Lund University, Sweden, a partner of the project.
Being able to control the direction of growth means that researchers can tune various physical properties such as bandgap, refraction index, thermal and electrical conductivity, and piezoelectric polarisation.
This concept looked at hybrid technology based on the formation of silicon nanowires by etching, followed by epitaxial growth of, for instance germanium.
‘But silicon technology becomes very challenging when you get down to 10-15nm,’ explains his colleague Lars Samuelson, Director of the Nanometer Structure Consortium at Lund University and coordinator of the NODE project.
‘One of the problems of the top-down approach is that it introduces harsh environments and you end up with devices that may be dominated by defects.’
The NODE researchers dry etch hole patterns on silicon for constrained growth of nanowires, without using a catalyst. A template is prepared by lithography patterning of a plasma-enhanced chemical-vapour deposited 300nm silicon oxide film stack with openings to expose the underlying silicon. The etching technique can shrink printed feature sizes thanks to a polymeric coating deposited on the developed resist. Particular care is taken to clean the side walls and the bottom silicon substrate to avoid defects during growth.
‘We call it “guided self-assembly”, and it gives more uniform nanowire surfaces,’ says Samuelson. ‘Vertical nanowires can consist of different materials, by altering the depositing material, so the wire takes on layers with different characteristics.’
This vertical arrangement may be the route to 3D circuit design as well as monolithic on-chip optoelectronics.
X-ray diffraction gives information about crystallo-graphic phases, stacking defects and epitaxial relationships with orientation distributions.
Electronics giant IBM Research, based in Rüschlikon, Switzerland, one of many partners on the project, stresses that they are still some way from seeing the technology in application.
‘Good control over wire growth has been achieved, but further processing is required to
integrate nanowires into functional devices,’ explains Dr Heike Riel, Manager of Nanoscale Electronics at IBM Research.
‘After growth, the wire surface needs to be properly passivated by thermal oxidation by conformal atomic layer deposition of a high-K material serving as gate dielectric.
‘Nanowire technology will gradually find its place by offering advantages such as the potential for wrap gates, 3D integration, and the ability to grow heterostructures of materials with large lattice mismatch.’Materials World Magazine, 01 Mar 2010
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