Better chip design
Semiconductor manufacturers are attempting to achieve more robust silicon chips with faster time-to-market and higher yield during production at the nanoscale.
As part of a project named Robust Design for Efficient Use of Nanometre Technologies, Infineon, NXP Semiconductors and STMicroelectrics have refined models and validated the design flows and measurement techniques (on-chip and off-chip). The research has led to specifications for electronic design automation tool providers.
To guarantee circuit robustness below 90nm, the partners have considered a panel of dangers that threaten signal integrity, including power degradation and internal couplings within the chip, chip-package interactions, and problems associated with the external environment such as soft error rates and electrostatic discharges.
In most cases engineers exploit simulations to predict the behaviour of the chips. However, a simulation is only as good as the algorithm it models, resulting in the possibility of over or under design, with the chip failing when manufactured in silicon.
Modelling challenges are compounded by smaller feature sizes. A 45nm transistor, for example, shows some additional physical effects, usually second- or third-order effects, which are not visible in 130nm or 90nm transistors.
Dr Thomas Brandtner of Infineon Technologies Chip Package-Board Codesign in Villach, Austria, says, ‘Intra-block coupling and natural radiation effects were studied to improve design methodology and simulations tools with respect to undesired coupling impacting only one block.
This included a better modelling of parasitic behaviour of package routing and an easy integration of those models into an overall chip/system simulation. In addition, improved simulation models for electrostatic discharge events were generated’.
The research led to newly developed accurate path resistance extraction, which runs 30 times faster than before. Furthermore, the parametric yield was improved by reducing errors at low voltage from 16,000 for a 65nm static random access memory to none and circuit speed is said to have been increased up to eight gigagertz on silicon.
The researchers looked into improved digital TV power grid design, automotive power noise experiments, wireless substrate noise interference, multimedia accelerators for mobile platforms and telecom pulse width.Materials World Magazine, 01 Jan 2010
As part of a project named Robust Design for Efficient Use of Nanometre Technologies, Infineon, NXP Semiconductors and STMicroelectrics have refined models and validated the design flows and measurement techniques (on-chip and off-chip). The research has led to specifications for electronic design automation tool providers.
To guarantee circuit robustness below 90nm, the partners have considered a panel of dangers that threaten signal integrity, including power degradation and internal couplings within the chip, chip-package interactions, and problems associated with the external environment such as soft error rates and electrostatic discharges.
In most cases engineers exploit simulations to predict the behaviour of the chips. However, a simulation is only as good as the algorithm it models, resulting in the possibility of over or under design, with the chip failing when manufactured in silicon.
Modelling challenges are compounded by smaller feature sizes. A 45nm transistor, for example, shows some additional physical effects, usually second- or third-order effects, which are not visible in 130nm or 90nm transistors.
Dr Thomas Brandtner of Infineon Technologies Chip Package-Board Codesign in Villach, Austria, says, ‘Intra-block coupling and natural radiation effects were studied to improve design methodology and simulations tools with respect to undesired coupling impacting only one block.
This included a better modelling of parasitic behaviour of package routing and an easy integration of those models into an overall chip/system simulation. In addition, improved simulation models for electrostatic discharge events were generated’.
The research led to newly developed accurate path resistance extraction, which runs 30 times faster than before. Furthermore, the parametric yield was improved by reducing errors at low voltage from 16,000 for a 65nm static random access memory to none and circuit speed is said to have been increased up to eight gigagertz on silicon.
The researchers looked into improved digital TV power grid design, automotive power noise experiments, wireless substrate noise interference, multimedia accelerators for mobile platforms and telecom pulse width.Materials World Magazine, 01 Jan 2010
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